1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for forming a textured surface on a semiconductor substrate by an over-thermal oxidation process and forming a tunneling oxide layer on the textured surface.
2. Description of Related Art
In order to fabricate a memory device with high density and low cost so as to satisfy a marketing desires, an electrically erasable programmable read only memory (EEPROM) is developed for the purpose. The EEPROM uses a Fowler-Nordheim tunnel effect to program or erase binary data stored in the EEPROM. The programming/erasing operation is done bit by bit so that it takes time. Another faster memory device, called flashing memory, is also developed. The flash memory has similar structure as the EEPROM but the programming and erasing functions are performed through block by block.
It is a trend for a semiconductor device to have a low operating bias so that the EEPROM or the flash memory also need a low operating bias. In order to have the low operating bias, it is necessary to have a tunneling oxide layer with properties of high electron injection efficiency and high duration of charge to breakdown (Q.sub.bd). The tunneling oxide layer used in the EEPROM with low operating bias is necessary to be formed on a substrate with textured surface so that the thickness of the tunneling oxide layer is not necessary to be thinned.
A conventional fabrication process for forming a tunneling oxide layer on a semiconductor substrate with textured surface is schematically shown in FIGS. 1A-1C. In FIG. 1A, a semiconductor substrate 100, such as a silicon substrate, is provided. In FIG. 1B, a reactive ion etching (RIE) process is directly performed on the substrate 100 so as to form a substrate 102 with textured surface. In FIG. 1C, a tunneling oxide layer 104 is formed over the substrate 102.
However, as the RIE process is performed, the plasma source may easily cause plasma damage and plasma contamination to affect the tunneling oxide layer 104, resulting in a poor performance of the EEPROM. Moreover, the RIE process including the reaction etchant gas, the pressure of the etchant gas, the power of plasma source, and several processes for fixing the plasma damage and cleaning the plasma contamination is complicate, resulting in a difficulty of use.
FIGS. 2A-2B are cross-sectional views of a portion of a semiconductor substrate, schematically illustrating an another fabrication process for forming a tunneling oxide layer on the semiconductor substrate with textured surface. In FIG. 2A, a semiconductor substrate 200 is provided. A polysilicon layer 202 is formed over the substrate 200 by low pressure chemical vapor deposition (LPCVD). In FIG. 2B, a thermal oxidation is performed on the polysilicon layer 202. The thermal process is necessary to be property controlled so as to just fully oxidize the polysilicon layer 202. Since the polysilicon layer 202 includes large number of polycrystals and grain boundaries between polycrystals, the polycrystals and the grain boundaries have different oxidation rate. After the thermal oxidation process a textured structure is automatically formed. The polysilicon layer 202 and the substrate 200 of FIG. 2A respectively become a textured oxide layer 206 and a textured substrate 204. A textured surface exists at the interface between the textured oxide layer 206 and the textured substrate 204. The textured oxide layer 206 serves as a conventional another tunneling oxide layer. Several subsequent structures (not shown) are then formed over the textured substrate 204 to accomplish a memory fabrication.
However, in the above another conventional example, the duration time of the thermal oxidation process should be precisely controlled to just oxidize the polysilicon layer 202. If an incomplete oxidation occurs, a performance of the tunneling oxide layer is deteriorated due to remaining polysilicon without being oxidized. The performance of the tunneling oxide layer is also deteriorated if an over oxidation occurs, causing the textured substrate 204 is over oxidized. Since the polysilicon layer 202 usually is very thin, it is difficult to control the oxidation rate and the duration time to just completely oxidize the polysilicon layer 202. This causes a complexity of this conventional method.
All above two conventional methods have their drawbacks. The first conventional example has issues of plasma damage and plasma contamination. The second conventional example has a difficulty to control the oxidation rate and the oxidation duration time.